If a port name changes, the software assigns a related user logic name in the design or a generic port name such as IN1 or OUT1. For example, the software removes ports that are unconnected or driven by GND or V CC during synthesis. However, the software may change or remove port names from the design. Where possible, the Intel® Quartus® Prime software maintains the port names of each hierarchy throughout synthesis. For supported device families, you can also view internal registers and look-up tables (LUTs) inside logic cells (LCELLs), and registers in I/O atom primitives. The Technology Map Viewer shows the hierarchy of atom primitives (such as device logic cells and I/O ports) in the design. The Intel® Quartus® Prime Technology Map Viewer provides a technology‑specific, graphical representation of FPGA designs after Analysis and Synthesis or after the Fitter maps the design into the target device.
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